Search - maxplus a

[Other resource] pulse_change

Description: 用vhdl实现脉冲宽度可控的一简单程序仿真环境MAXPLUS--use VHDL to achieve controllable pulse width of a simple process simulation environment Segments-
Platform: | Size: 183569 | Author: dm | Hits:

[VHDL-FPGA-Verilog] FIR低通滤波器部分模块

Description: 一个FIR低通滤波器,最小阻带衰减-30db,带内波动小于1db．用MAXPLUS2设计与仿真。-This is a FIR LPF, with-30dB in stop-band and sigma is less than 1dB. It is designed and simulated on MAXPLUS2.
Platform: | Size: 5120 | Author: 吴健宇 | Hits:

[Books] max+plus ii快速入门

Description: maxplus2是一款应用于硬件编程的编程软件，本文件教你快速掌握其编程，仿真方法。-maxplus2 hardware is a programming application programming software, this document will teach you grasp its programming and simulation methods.
Platform: | Size: 344064 | Author: 刘晓飞 | Hits:

[Other] wave0001

Description: 在MAX-PLUS下设计的函数消耗发生器，波形有正弦波、方波、三角拨、锯齿波（用键盘选择），信号频率可调（用键盘调节）-the MAX-PLUS design of the consumption function generator, a sine wave, square, triangle area and Sawtooth (keyboard), in signal frequency adjustable (keyboard conditioning)
Platform: | Size: 133120 | Author: 曹海学 | Hits:

[VHDL-FPGA-Verilog] 脉冲记时CPLD

Description: 工作原理：脉冲输入，记录30个脉冲的间隔时间（总时间），LED显示出来，牵涉到数码管的轮流点亮，以及LED的码。输入端口一定要用个 74LS14整一下，图上没有。数码管使用共阴数码管。MAXPLUS编译。测试时将光电门的信号端一块连接到J2口的第三管脚，同时第一管脚为地，应该与光电门的地连接（共地）。开始测试：按下按键，应该可以见到LED被点亮，指示可以开始转动转动惯量盘，等遮光片遮挡30次光电门后， LED熄灭，数码管有数字显示，此为时间值，单位为秒，与智能计时器的连续脉冲测试模式中的T30值进行比较。再按下按键即可进行下一次测量。水平有限，见笑。-principle : pulse input, recording 30 pulse interval (total time), the LED display and digital control involves rotating lights, and LED yards. Input port must use the entire 000 74LS14 that there is no map. Digital control the use of digital control were overcast. Segments compiler. Test the door to the photoelectric signal an end connected to the mouth of the third J2 pins, for the first pin, should the photoelectric doors to connect (to a total). Testing : press the button, should be able to see the LEDs are lit, instructions to start the rotation inertia set, films such as shading block 30 photoelectric doors, the LED is off, digital possession figures show that for the time value of this unit for seconds Intelligent timer with a continuous pulse mode testing of T30 values were compare
Platform: | Size: 645120 | Author: 高颖峰 | Hits:

[VHDL-FPGA-Verilog] FIRvhdl

Description: 用vhdl实现一个fir滤波器设计要求： 1．最小阻带衰减-30db。 2．带内波动小于1db． 3．用MATLIB与MAXPLUS2联合设计与仿真-use VHDL to achieve a fir filter design requirements : 1. The smallest stop band attenuation- 30dB. 2. With fluctuating within less than 1DB. 3. With MATLIB with MAXPLUS2 joint design and simulation
Platform: | Size: 3072 | Author: 达闻西 | Hits:

[VHDL-FPGA-Verilog] EDAchuzuchejijia

Description: 在本示例程序中，用VHDL语言实现了出租车的记价功能，在Maxplus2环境下编写，可通过cpld下载板来验证程序。在压缩包中附有示例的目的，方法和仿真时序图，是学习VHDL好例子。-in this sample program, using VHDL of the entry price of a taxi function, in preparation FLEX10K environment, through cpld download plate to the verification process. The compression package with the purpose of example, the simulation methods and timing diagrams, is a good example to learn VHDL.
Platform: | Size: 339968 | Author: bkd | Hits:

[VHDL-FPGA-Verilog] clock_CPLD

Description: 采用MaxPlusII写的一个小时钟程序，也是供初学参考。呵呵。注///版主，开发环境里面没有MaxPlusII.-MaxPlusII used to write a small clock procedures, as well as reference for beginners. Ha ha. Note///moderator, development environment there's no MaxPlusII.
Platform: | Size: 812032 | Author: Backy | Hits:

[VHDL-FPGA-Verilog] MAXplusqiangda

Description: MAXplus抢答器课程设计做了很久的验证通过-MAXplus Responder course design a long time ago passed the test
Platform: | Size: 1024 | Author: 侧卫 | Hits:

[VHDL-FPGA-Verilog] clock_VHDl

Description: 一个初学者写的时钟程序，VHDL语言，MAXPLUS环境。-The clock to write a beginners program, VHDL language, MAXPLUS environment.
Platform: | Size: 6144 | Author: 朱涛 | Hits:

[VHDL-FPGA-Verilog] eda

Description: 来自某名牌大学电子实验室的eda指导教程，主要介绍了maxplus2，适合初学者-From a prestigious university guide EDA Electronic lab tutorials, mainly the introduction maxplus2, suitable for beginners
Platform: | Size: 484352 | Author: xiaoshuai | Hits:

[Other] MAXPLUS2

Description: EDA课程所用的Max Plus2软件，制作的半加器，有图像文件，有波形文件，建议看看，-EDA courses used by Max Plus2 software, produced a half-adder, there are image files, documents have waveform, it is recommended to see,
Platform: | Size: 31744 | Author: jimchen | Hits:

[VHDL-FPGA-Verilog] MAXplus

Description: MAXplusⅡ入门与提高.rar 一本很经典的入门书我们老师推荐的-MAXplus Ⅱ entry and improving. Rar is a classic primer recommended by our teachers
Platform: | Size: 12635136 | Author: twinslizzy | Hits:

[Software Engineering] 07302529

Description: 计算机组成原理实验（MAX PLUS） 1.ALU设计 2.MEM设计 3.32位2选1选择器-Principles of Computer Organization Experiment (MAX PLUS) 1.ALU design 2.MEM design 3.32 2 election 1 selector
Platform: | Size: 244736 | Author: 翁浩达 | Hits:

[VHDL-FPGA-Verilog] MAXPLUS

Description: 一个非常有用的CPLD开发程序，对开发有兴趣的你们，赶快进来吧-A very useful CPLD development process of the development you are interested, hurry Come
Platform: | Size: 905216 | Author: haongodng | Hits:

[VHDL-FPGA-Verilog] MAXPLUS

Description: 这是一本介绍MAXPLUS的书，讲的浅显易懂，希望对大家有点用-This is an introductory book MAXPLUS, talk about easy to understand, I hope all of you a bit with
Platform: | Size: 267264 | Author: wyq | Hits:

[VHDL-FPGA-Verilog] My_Clock

Description: 发个我的第一个VHDL代码，秒表。可暂停继续.清0。-My first one made a VHDL code, and a stopwatch. Continue to be suspended. Qing 0.
Platform: | Size: 585728 | Author: jemofh | Hits:

[Other Embeded program] CPUsourcecode

Description: 本设计实现了一个具有标准的32位5级流水线架构的MIPS指令兼容CPU系统。具备常用的五十余条指令，解决了大部分数据相关，结构相关，乘除法的流水化处理等问题，并实现了可屏蔽的中断网络。-This design implements a standard 32-bit 5-stage pipeline architecture of MIPS instruction compatible CPU system. Instructions with more than 50 commonly used to solve most of the data related to the structure related to the water processing multiplication and division problems, and realize the network that can shield the interrupt.
Platform: | Size: 93184 | Author: 李敏 | Hits:

[VHDL-FPGA-Verilog] dotmatrix

Description: MAXplus 2 课程设计点阵的动态显示-A programme of VHDL developed in MAXplus 2 to display one s name in a shifting way.
Platform: | Size: 1024 | Author: 刘进 | Hits:

[VHDL-FPGA-Verilog] fir

Description: 真正意思上的fir滤波器课程设计，基于quartus II9.0的vhdl代码。有原理图输入和例化元件-The real meaning of the fir filter design program, based on quartus II9.0 the vhdl code. A schematic of components and cases
Platform: | Size: 1439744 | Author: liyu | Hits:

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[Other resource] pulse_change

[VHDL-FPGA-Verilog] FIR低通滤波器部分模块

[Books] max+plus ii快速入门

[Other] wave0001

[VHDL-FPGA-Verilog] 脉冲记时CPLD

[VHDL-FPGA-Verilog] FIRvhdl

[VHDL-FPGA-Verilog] EDAchuzuchejijia

[VHDL-FPGA-Verilog] clock_CPLD

[VHDL-FPGA-Verilog] MAXplusqiangda

[VHDL-FPGA-Verilog] clock_VHDl

[VHDL-FPGA-Verilog] eda

[Other] MAXPLUS2

[VHDL-FPGA-Verilog] MAXplus

[Software Engineering] 07302529

[VHDL-FPGA-Verilog] MAXPLUS

[VHDL-FPGA-Verilog] MAXPLUS

[VHDL-FPGA-Verilog] My_Clock

[Other Embeded program] CPUsourcecode

[VHDL-FPGA-Verilog] dotmatrix

[VHDL-FPGA-Verilog] fir

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